Design verification (checking if the design is correct) and manufacturing testing (checking if the hardware was built correctly) are two different worlds. Even a perfect design can suffer from physical defects like shorts, opens, or CMOS imperfections during fabrication.
The most traditional model is the , where a circuit node is assumed to be permanently stuck at logic 0 (SA0) or logic 1 (SA1). While this model does not perfectly capture all physical defects (like bridging or delay faults), it remains the industry standard for structural testing because test generation algorithms for SAFs are highly mature. digital systems testing and testable design solution